Modern integrated circuits typically include millions of transistors. Most commonly these transistors are field effect transistors (FETs). These transistors are typically not identical throughout an integrated circuit, but rather are divided into categories that are based on ranges of various physical, material, electrical, and quantum mechanical properties or characteristics. The aforementioned categories are referred to herein as transistor device types. Illustrative transistor device types that are commonly found in integrated circuits include, but are not necessarily limited to: p-channel FETs, n-channel FETs, FETs tailored for digital or analog circuit applications, high-voltage FETs, high/normal/low frequency FETs, FETs optimized to mimic older FET designs (i.e., legacy FETs), FETs optimized to work at distinct voltages or voltage ranges, and low/high power FETs.
The speed at which FETs switch between conducting (i.e., on) to non-conducting (i.e., off) states is typically related to the threshold voltage (Vt) associated with those FETs. For example, a transistor having a low Vt may switch faster than a transistor having a higher Vt. For speed critical applications, one might be tempted to consider using only transistors having a low Vt. However, one drawback of a low Vt transistor is undesirably high off-state leakage current. Therefore, circuit designers typically optimize an integrated circuit design for, among other things, off-state leakage current by specifying a plurality of transistor device types, each device type having a different threshold voltage. Some transistors may be specified with low Vt, other transistors may be specified with regular Vt, while still others may be specified with high Vt, with various refined Vt settings therebetween. In mobile applications as well as certain desktop applications, space constraints and other factors drive the desire to use semiconductor chips having multiple Vt integrated circuits thereon, and there remains an ongoing interest to reduce the size of the integrated circuit blocks. At the same time, power reduction and extending battery life drive the desire to use efficient semiconductor chip designs having reliable switching. A way to achieve the combined product and circuit design goals is to design semiconductor devices, e.g., transistors, having a greater uniformity of electrical characteristics. For example, a tighter distribution of variations in Vt allow for efficient circuit designs. In this way, switching reliability is achieved, which in turn reduces the need to design in compensation circuitry. The reduced need to design in circuit redundancies can reduce the size of the integrated circuit blocks.
However, fabricating multiple Vt devices in silicon using conventional CMOS processes remains an ongoing challenge. For instance, to set Vt for an individual transistor in a conventional CMOS process while also optimizing for other detrimental factors such as short-channel effects, junction capacitance, drain-induced barrier lowering effects and other issues, process engineers typically use oppositely-doped implanted regions that jut outward of the source and drain and extending inward into the channel a defined distance. Such implanted dopant regions are known as “pocket” or “halo” implants. Usually the halo implant is achieved using a multi-step, controlled implantation that involves driving ionized dopant species into the silicon lattice at high energy. To remedy damage to the lattice structure that results, as well as to activate the dopants, an anneal is typically done. While controllability of the anneal step(s) and the resultant doping profile is generally understood, the process of driving implanted material into silicon at various angles comes with inevitable variation and challenges as to process control. Also, whenever dopants are introduced directly into the transistor channel, the dopants can exhibit random fluctuation in dopant placement and concentration which can adversely affect carrier mobility and corresponding Vt. A further challenge is to carry on such Vt setting techniques as critical dimensions continue to shrink. At these smaller gate lengths, even small fluctuations in the resultant shape of the halo implants affects the final Vt that is set for the transistor. It is therefore difficult to reliably set Vt across a plurality of transistors. A further complication occurs when such processes are applied for multiple transistor device types, each having different Vts. There then results not only the variation from transistor-to-transistor for the same type of transistors, but further variation across different transistor device types. Because of such limitations in the semiconductor process, circuit designers develop techniques and redundancies to compensate for the Vt variation which typically results in a larger cell footprint. Such compensatory designs are not straightforward, and serve to add to the cost of producing an integrated circuit, particularly at the more advanced semiconductor processes.
What is needed are integrated circuits having multiple sets of transistor structures, each set with its own range of physical, material, electrical, and quantum mechanical properties or characteristics, and methods of integrating the manufacture thereof to result in a reduction in the variation of threshold voltage.